Implementasi Desain Sistem Digital: Simulasi Perancangan Sistem Teller Bank Berbasis FPGA

Resa Pramudita, Muhammad Adli Rizqulloh, Roer Eka Pawinanto, Carolina Patrycia Maryana, Muhammad Hasanul Fikri, Riana Sukma Dewi

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Sistem antrian elektronik merupakan sebuah perangkat elektronik yang sering digunakan di bank dan tempat umum lainnya yang memerlukan antrian seperti rumah sakit, puskesmas dll. Perancangan sistem ini biasanya dilakukan dengan menggunakan mikrokontroller. Pada penelitian ini sistem dirancang menggunakan FPGA. Penelitian ini bertujuan sebagai studi awal sebelum diimplementasikan ke dalam sistem ASIC dimana kelebihan dari sistem ASIC adalah dapat membuat desain sistem yang terintegrasi dalam satu IC dan memiliki fungsi spesifik. Selain itu penggunaan daya juga lebih rendah. Simulasi pada rangkaian ini menggunakan ModelSim dan untuk proses Synthesis menggunakan Quartus. Intelectual Property (IP) yang dirancang akan diimplementasikan pada device EP4CE6E22C8. IP Teller Machine memiliki 5 input dan 3 output. Arsitektur sistem yang telah dirancang hanya menggunakan daya sebesar 65.46mW. IP Teller Machine yang telah dibuat ini mampu menerima sinyal dengan frekuensi maksimal mencapai 206.53MHz. Counter 4 bit internal mampu menerima input sinyal dengan frekuensi mencapai 402.09MHz. IP Core yang telah dirancang ini selain dapat digunakan untuk Teller Machine dapat juga digunakan sebagai Multiple Input High Speed Counter.

 

An electronic queuing system is an electronic device often used in banks and other public places requiring queuing, such as hospitals, health centers, etc. The design of this system is usually done using a microcontroller. In this study, the system was designed using FPGA. This research is intended as an initial study before it is implemented into the ASIC system, where the advantage of the ASIC system is that it can make a system design that is integrated with one IC and has specific functions. In addition, the power usage is also lower. Simulation on this circuit uses ModelSim, and the Synthesis process uses Quartus. The designed Intellectual Property (IP) will be implemented on the EP4CE6E22C8 device. IP Teller Machine has 5 inputs and 3 outputs. The system architecture that has been designed uses only 65.46mW of power. The IP Teller Machine that has been made can receive signals with a maximum frequency of up to 206.53MHz. The internal 4-bit counter can receive input signals with frequencies up to 402.09MHz. Apart from being used for Teller Machines, the IP Core that has been designed can also be used as a Multiple Input High-Speed Counter.


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IP; FPGA; ASIC; counter; teller

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Referensi


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DOI: https://doi.org/10.15575/telka.v9n1.22-33

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